Embodiments of the present invention relate to semiconductors, and more particularly to semiconductor packaging technology.
Today's integrated circuits (ICs) are manufactured with increasingly higher performance, reduced costs, and increased miniaturization of components and devices. Accordingly, packaging for such ICs is also subject to ongoing shrinkage of form factors. Some ICs such as processors, controllers, logic devices, memory devices and the like may be housed in a package including a substrate having internal electrical connections to the semiconductor die, along with other components. The package further includes external electrical connections to enable the package to be electrically connected to, for example, a circuit board such as a motherboard or the like, either directly or indirectly.
As semiconductor devices and corresponding semiconductor packages continue to shrink, many issues arise. For example, when the thickness of a substrate of a semiconductor package shrinks, substrate coplanarity/warpage challenges can exist during assembly operations. To attempt to overcome such problems, a package can be molded to improve its stiffness. However, in applying a molding to such a package, concern must be taken to avoid molding over a semiconductor die within the package. That is, an exposed-die mold configuration is typically used in which the mold layer and the exposed portion of the semiconductor die (typically a backside) are substantially coplanar. This coplanarity allows the die to be exposed, as the die, which can include various semiconductor devices such as processors, functional units, memories and the like, radiates significant heat during operation. An exposed die improves heat dissipation performance, as a heat sink or other thermal dissipation mechanism can be directly coupled to the die. This direct contact allows heat from the die to be effectively thermally coupled to the thermal dissipation mechanism.
However, an exposed-die molded package in packaging having a small form factor (e.g., thickness) fails to meet planarity limitations and thus still suffers from warpage problems. Such warpage issues are exacerbated during stress testing, such that mold-to-substrate delamination occurs after such stressing due to excessive package warpage.
Accordingly, a need exists for improved semiconductor packaging techniques.